1. Field of the Invention
The present invention relates generally to field emitter cells and arrays. More specifically, the present invention relates to low gate current thin-film-edge emitter cells and arrays.
2. Description of the Background Art
Very small localized vacuum electron sources which emit sufficiently high currents for practical applications are difficult to fabricate. This is particularly true when the sources are required to operate at reasonably low voltages. Presently available thermionic sources do not emit high current densities, but rather result in small currents being generated from small areas. In addition, thermionic sources must be heated, requiring special heating circuits and power supplies. Photo emitters have similar problems with regard to low currents and current densities.
Field emitter arrays (FEAs) are naturally small structures which provide reasonably high current densities at low voltages. FEAs typically comprise an array of conical, pyramidal or cusp-shaped point edge or wedge-shaped vertical structures which are electrically insulated from a positively charged extraction gate and which produce an electron beam-that travels through an associated opening in the charged gate.
The classical field emitter includes a sharp point at the tip of the vertical structure and opposite an extraction electrode. In order to generate electrons which are not collected at the extraction electrode, but can be manipulated and collected somewhere else, an aperture is created in the extraction electrode which aperture is significantly larger (e.g. two orders of magnitude) than the radius of curvature of the field emitter. Thus, the extraction electrode is a flat horizontal surface containing an extraction electrode aperture for the field emitter. The field emitter is centered horizontally in the extraction electrode aperture and does not touch the extraction electrode, although the vertical direction of the field emitter is perpendicular to the horizontal plane of the extraction electrode. The positive charges on the edge of the extraction electrode aperture surround the field emitter symmetrically so that the electric field produced between the field emitter and the extraction electrode causes the electrons to be emitted from the field emitter in a direction such that are collected on an electrode (anode) separate and distinct from the extraction electrode. A very small percentage of the electrons are intercepted by the extraction electrode. The smaller the aperture, i.e., the closer the extraction electrode is to the field emitter, the lower the voltage required to produce field emission of electrons.
It is difficult to create FEAs which have reproducibly small radius-of-curvature field emitter tips of conducting materials or semiconducting materials. Furthermore, it is equally difficult to gate or grid these structures where the gate-to-emitter distance is reasonably small to provide the necessary high electrostatic field at the field emitter tip with reasonably small voltages. The radius of curvature is typically 100-300 angstroms (Å) and the gate-to-emitter distance is typically 0.1-0.5 micrometers (μm).
Current methods of manufacturing FEAs include wet etching, reactive ion etching, and a variety of field emitter tip deposition techniques. Practical methods generally require the use of lithography which has a number of inherent disadvantages including the high cost of the equipment needed. Furthermore, the high degree of spatial registration requires expensive high resolution lithography.
To a large extent, these prior art problems were overcome by Hsu et al., U.S. Pat. No. 5,584,740 and Gray et al., U.S. Pat. No. 5,382,185, both of which are incorporated herein by reference for all purposes in their entirety. The '740 and '185 patents describe a thin-film-edge emitter cell including a substrate having a protuberance extending therefrom, a conformally deposited insulating layer over the substrate and vertical sidewall of the protuberance, an emitter film conformally deposited upon the insulating layer and the vertical sidewall thereof, and a gate metallization layer parallel to the vertically extending portion of the emitter film. The emitter film extends vertically beyond the protuberance. U.S. Pat. Nos. 5,214,347 and 5,266,155 to Gray, both are which are incorporated-by-reference herein in their entirety for all purposes, describe horizontal thin-film edge field emitters and gated field emitters.
Because of the parallel orientation of the emitter film relative to the gate, the insulating layer between these elements in those patented devices must be sufficiently thin so that, at the emitter tip, the gate generates a field capable of extracting electrons at the tip. The dependence of the gate to tip distance upon insulating film thickness requires a trade off between the reduced susceptibility to pinhole defects and voltage breakdown offered by thicker a insulating films and the increased voltage demands caused by the resulting additional gate to tip distance. Additionally, the parallel orientation of the gate layer creates a high capacitance. In turn, this high capacitance increases the RC time constant, reducing frequency response and power efficiency.
Commonly-owned U.S. application Ser. No. 09/045,853 filed on Mar. 23, 1998, which is incorporated herein by reference in its entirety, describes an improved field emitter cell/array that can potentially surpass the current conical or pyramidal tip FEAs both in terms of performance and cost. In particular, the FEAs described in the '853 application provides various performance advantages including higher emission current, lower voltage, lower capacitance, higher transconductance, resistance to “poisoning” by ambient gas, resistance to oxidation and resistance to blunting by back-ion bombardment. In fact we have found that the FEAs of the '853 application has better oxidation resistance than any FEA known to date. Furthermore, the FEAs of the '853 application can be manufactured at relatively low cost as compared to prior devices. For example, the manufacture of FEAs of the '853 application requires only about one-third as many processing steps as the conical tip FEAs. In addition, lithography can be replaced with stamping technology in making the one-step masks for producing the starting template structures described in the '853 application.
However, the FEAs disclosed in the '853 application typically exhibit gate currents of about 7 to about 15% of the anode current. Although gate currents of these sizes are acceptable for applications that involve tow currents and low power levels (e.g., field emitter displays), they cannot be tolerated in applications that require high currents and high power levels (e.g., power switching, microwave, and millimeter wave power amplifiers). Specifically, power dissipation cat greater than about 1% gate current would damage the FEA.